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[Hide] (17.8KB, 236x283) Android has been ported to a RISC-V board
January 21, 2021
Google’s Android operating system currently supports a handful of instruction set architecture (ISA) families, including ARM and x86. The vast majority of smartphones, tablets, TVs, and smartwatches that run Android today feature ARM-based chipset designs, as Intel has long since abandoned its handset CPUs while support for MIPS was dropped with NDK revision 17. While Google does not officially provide support for compiling Android on hardware based on the open RISC-V ISA, several development teams are working to run AOSP on RISC-V hardware. One such effort is led by T-Head, the business entity of Alibaba specializing in semiconductors, which today announced that they’ve successfully ported Android 10 onto its in-house RISC-V hardware.
A few months ago, PLCT Lab successfully booted Android to a command-line interface on a 64-bit RISC-V core emulated in QEMU. The team launched a project on GitHub they’re calling “AOSP for RISC-V” and are still in the early stages of cross-compiling AOSP and booting to a GUI. Meanwhile, T-Head, which designed the ICE SoC with its in-house, RISC-V-based XuanTie C910 cores, has managed to boot Android 10 with working graphics and touch.
The ICE chip from T-Head with 3 XuanTie C910 (RISC-V 64) CPU cores.
It runs quite slowly, as you can see in the video embedded below, but this is to be expected given the status of this port and the hardware it’s running on. In the video, a couple of stock AOSP applications are launched, including the clock app, the contacts app, and the mail app. More complex applications such as games aren’t shown off on this prototype as these apps would likely need to be recompiled to target RISC-V.
https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/registerUrl/undefined/1611216336818/normal_video121.mp4
This Android 10 port is based on the android10-release branch in AOSP, and the source code developed by T-Head can be found on the company’s GitHub page.